Computers are ubiquitous in today's society. They come in all different varieties and can be found in places such as automobiles, laptops or home personal computers, banks, personal digital assistants, cell phones, as well as many businesses. In addition, as computers become more commonplace and software becomes more complex, there is a need for the computing devices to perform at faster and faster speeds in smaller and smaller packages. For example, newer microprocessors often have higher operating frequencies than previous generations of microprocessors, which often results in an increase in processing power for the processor.
Microprocessors that operate at a high frequency typically have some high frequency clock generator circuitry that generates a high frequency clock signal that is used to pace the operation of the microprocessor. This high frequency clock signal is then transmitted throughout the microprocessor chip on high frequency wires or lines on the chip. This collection of high frequency signal paths in the microprocessor design is known as the fan out of the clock signal. However, such high frequency paths in the chip are often costly, both in terms of utilized chip area, hardware costs and power consumed, as well as being more complicated to design. Such costs have typically been accepted during the design of microprocessors, though, as synchronization between the various components of the microprocessor is crucial to the proper operation of the device.
Thus, techniques are described herein to reduce the number and length of high frequency signal paths in a microprocessor design to provide a cost and power savings over previous microprocessor designs while maintaining synchronization between the various components of the microprocessor.
It is with these and other issues in mind that various aspects of the present disclosure were developed.